Tuesday, November 22, 2011

Intel to add TRIM support for RAID 0 in upcoming drivers

Intel to add TRIM

One of the barriers to using SSDs in RAID setups, other than the high price of the drives themselves, has been the lack of TRIM support when running in that mode. TRIM is a command that allows an OS like Windows 7 to inform an SSD which blocks of data can be wiped and marked for re-use. This process, sometimes referred to as garbage collection, mitigates the performance degradation that inevitably occurs as an SSD becomes “dirty.”

It’s been difficult to add TRIM support to RAID controllers because they weren’t historically designed to do so; standard hard drives don’t need to differentiate between blocks of data that have actually been erased, versus those that have simply been marked as erasable. To date, TRIM has been incompatible with RAID controllers. Various manufacturers, including Intel, have claimed to be working on the problem for years, but with precious little to show for it — until now. According to the folks at StorageReview, a note inside Intel’s 11.5 Alpha Rapid Storage Technology (RST) drivers states: “This release will not enable the TRIM on RAID0 feature, but it will be added in the next RST 11.5 release.”

If so, it’s an important first step towards extending TRIM support across multiple RAID levels. SSD RAID 0 setups may find little use outside of the performance-crazed enthusiast market, but TRIM is equally important for anyone interested in a RAID 1 or RAID 5 configuration. The introduction of triple-cell level (TLC) drives next year may spark a fresh interest in RAID as a means of overcoming the lower performance such drives will offer, particularly if TRIM is available in RAID 0+1 configurations.

The wording of Intel’s driver tidbit implies that this functionality won’t be limited to certain chipsets; boards from the Core 2 era may also benefit from the changes. The drive controller portion of Intel’s southbridges hasn’t changed much in several years — hopefully this is a bit of functionality that’ll stretch across multiple chipsets.



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